<oai_dc:dc xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
  <dc:creator>Soeken, Mathias</dc:creator>
  <dc:creator>Roetteler, Martin</dc:creator>
  <dc:creator>Wiebe, Nathan</dc:creator>
  <dc:creator>De Micheli, Giovanni</dc:creator>
  <dc:date>2017</dc:date>
  <dc:identifier>https://sonar.ch/global/documents/282343</dc:identifier>
  <dc:language>eng</dc:language>
  <dc:relation>info:eu-repo/semantics/altIdentifier/doi/10.1145/3061639.3062261</dc:relation>
  <dc:source>Proceedings of the 54th Annual Design Automation Conference 2017. - ACM. - 2017</dc:source>
  <dc:title xmlns:ns0="xml" ns0:lang="en">Hierarchical Reversible Logic Synthesis Using LUTs</dc:title>
  <dc:type>http://purl.org/coar/resource_type/c_6501</dc:type>
</oai_dc:dc>