Bachelor thesis

2D hardware acceleration

SONAR|HES-SO

    2017

Mémoire de bachelor: Haute Ecole d'Ingénierie, 2017

English The objective of the project is to develop an IP-core that provides hardware acceleration for common 2D rendering operations in an embedded system. The requirements for graphical user interfaces (GUI) on modern display and touchscreen based systems are increasing steadily. Rendering complex and attractive GUIs requires a lot of processing power. At the same time, energy consumption for most of these embedded systems should decrease. Being able to off-load processor intensive tasks such as rendering of 2D shapes to dedicated hardware vastly decreases rendering time and frees a lot of processor resources which leads to a faster GUI and a less power consuming system.
Language
  • French
Classification
Electronics
Notes
  • Haute Ecole d'Ingénierie Valais
  • Systèmes industriels - Systemtechnik
  • Infotronics
  • hesso:heivs
License
License undefined
Identifiers
  • RERO DOC 309194
Persistent URL
https://sonar.ch/global/documents/317362
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